The start of a typical method to obtain an EPROM memory eventually results in the product shown on FIG. 1A (sectional view) and shown on FIG. 1B (top view). By means of a thermal oxidation, insulating zones of field oxide (2) are made to increase over the upper surface of a silicon substrate (1) according to the LOCOS method. The insulating zones (2) have a variable thickness which reduces at their extremities and increases both inside and outside the substrate (1) so that the upper face of the substrate (1) loses its evenness, the parts between the insulating zones 2 being recessed. Then successively formed are a lower insulating oxide layer (3), for example, by thermal growth of the substrate, and a conductive layer of the polycrystalline silicon so as to constitute the floating gates. After these layers have been formed, the polycrystalline silicon layer is etched by photolithography techniques so as to embody openings in this layer above the insulating zones (2). An intermediate insulating oxide layer (5) is then deposited above the etched polycrystalline silicon layer (4) and on its flanks, then a second polycrystalline silicon layer (6), designed to compose the control gates, is deposited on the unit.
The following stages consist of etching by photolithographic techniques the unit formed by the layers 6, 5, and 4 along strips parallel to the cutting plane of FIG. 1A as far as layer 3. The regions of sources (7) and drains (9) are established at the etched locations. Then an upper oxide layer is deposited and subjected to a thermal flow and then to an etching by photolithographic techniques so as to embody contact openings (8) on the sources and drains (the layer 3 being etched during this etching). The lines of connections to the sources and drains (feed lines and lines of binary elements) are then installed on the upper oxide layer. As the upper oxide layer is deposited on a contorted surface, it is thus unable to any longer comprise a flat upper surface, even after the plastic flow, which complicates the installing of the electrical connection lines and renders this extremely difficult if the relief irregularities are too numerous, in other words, if the memory points of the memory are too close to each other. In addition, photolithography cannot be effected with perfect alignment; it is thus essential to take account of alignment defects or centerings by increasing the distance between the contact opening zones (8) and the surrounding conductive layers 4 and 6, or, in other words, by spacing the strips of the control gates, by locally deflecting them (as shown on FIG. 1B) so as to have pass at a distance the contact opening zones (8), or by foreshortening them at these locations. The documents DE-A1-35 42 939, EP-A2-0 182 198 and EP-A2-0 024 735 form part of this prior art. As a result from such dispositions, the integration density of memory points is rather small (the second and third documents respectively indicate, as an example, surfaces of 25 micrometers square and 18.5 micrometers by 13.5 micro-meters for each memory point.
U.S. Pat. No. 4,597,060 describes another type of EPROM memory in which the number of lines of electrical connections is especially reduced at the top of the circuit, having regard to the fact that the lines of binary elements coincide with the drains and the feed lines coincide with the sources. In this conception, there are no field oxide insulating zones on the substrate: the entire surface of each floating gate is above the conductive sections of the substrate. As a result, the ratio of the total capacity of a memory point is smaller for an interface surface between a given control gate and floating gate, which adversely affects the programming properties of the memory. Furthermore due to the fact that each drain is in contact with two rows of memory points, the stray currents are more considerable. Furthermore, this patent teaches a method of improving the planarization of semiconductor memory devices. It does not instruct one skilled in the Art, however, in any means of preventing the inadvertent electrical coupling of semiconductor memory conducting layers with contact openings.
Many processes are currently available in the art of semiconductor memory device manufacture to make contacts to substrate doped regions (e.g. source and drain contact openings) efficiently. For example, U.S. Pat. No. 4,507,853 describes a process in which semiconductor metallization patterns are deposited in such a manner as to avoid thinning at device steps and contact openings, resulting in lower contact opening-interconnection resistances and improved signal transmission. However, this patent does not teach a means of preventing inadvertent contact opening-conducting layer bonding during a metallization step; the patent does not even address itself to that concern.
Furthermore, U.S. Pat. No. 4,641,420 teaches a process involving overlaying a dielectric layer with a "smoothing" material, anisotropically etching this smoothing layer to remove it from all parts of the device except the sidewalls of the contact opening. A conducting material is then deposited over the surface of the device to make subsequent connections to the contact opening easier. This patent in no way solves the prior art's conductive layer-contact opening bonding problem. Moreover, the device under consideration in this prior art has no conductive layers within the device, but rather only has one conducting layer--the one in contact with the contact opening.
U.S. Pat. No. 4,707,717 details a method for fabricating a semiconductor memory device. However, it does not address itself to the problem presented above nor present an anisotropic engraving method to solve it. Furthermore, this prior art teaches a fabrication method in which etching is performed by photolithography. As stated previously, alignment of the photoresist used in photolithography is subject to errors which can result in serious device performance degradation. The present invention, therefore, teaches a process which is foreign to this prior art.
In the prior art, therefore, there is no disclosed method using anisotropic etching to prevent unintentional short circuiting of contact openings to one or more conducting layers, during metallization. Furthermore, any technique utilizing photolithography or masks runs the risk of photoresist or mask misalignment with the hazards inherent in such misalignment. The primary hazards of such misalignment are that either important device features will be etched inadvertently (possibly resulting in a defective device) or that large amounts of device surface area must be devoted to featureless regions surrounding contact openings (making further integration more difficult). This invention solves the problem in the prior art of contact opening-conducting layer short circuits without running the risk of either inadvertent etching of important device features though photoresist or mask misalignment or of wasting precious device surface area by forcing the prudent designer into allocating more device surface area than is necessary.